Package Design Engineer at Kandou developing high-speed chip-chip link solutions in semiconductor industry. Collaborating with engineering and marketing teams on packaging requirements.
Responsibilities
Complete all Package design activities within the given time frame as defined by the project deliverables.
Complete Package design review processes with the Assembly subcons to ensure no design rule violations.
Liaise closely with the respective IC layout Engineers during Package design phase.
Complete verification of Electrical characteristics of the package and unit design using available SW Tools.
Ensure cost effective methodologies are incorporated into Kandou’s BGA substrate and LF designs (Multi Layer / Mechanical Drill / Plating Lines etc).
Provide support, guidance and instructions to Assembly / Package related activities, questions and issues.
Present detailed weekly reports of activities and progress to the cross-functional team.
Work with multi-functional groups including product design, engineering and marketing to ensure our package design/technology requirements are fully supported by Kandou’s assembly partners.
Requirements
Minimum 5 years experience in IC Package Design using Cadence APD / SIP.
Hands on experience using Cadence (Virtuoso / Extract IM / Power DC ) / Ansys SW Tools (SiWave / Q3D ) or similar tools.
Experience using AutoCAD tool.
Knowledge about various Electronic IC Packaging technology is a must.
Basic understanding of Thermal and Mechanical behaviour of IC Packages.
Basic understanding of IC physical layout is beneficial.
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