Develop educational content for corporate training, utilizing AI and modern methodologies for engaging learning experiences. Collaborate with legal experts to create accessible educational material.
About the role
- Engineer I - Design at Microchip Technology Inc, responsible for RTL-based block design and verification. Engaging in general RTL and ASIC development with a focus on high-speed design techniques.
Responsibilities
- Designing, simulating, and verifying various RTL-based blocks on our devices.
- General RTL and ASIC development.
- Detailed module design, performance analysis, and detailed design specification creation.
- Participate in the RTL implementation, synthesis, simulation, pre-layout/post-layout timing verification.
- Understanding of emerging high speed design techniques to improve Data & Command processing bandwidth, reduce latencies & increase reliability.
- Support porting the design into test chips and emulation platforms – experience with FPGA design and board implementation tools is advantageous.
Requirements
- Bachelor’s in Electrical Engineering, Computer Engineering or Computer Science.
- Design courses and practical application of course learning for high-speed RTL design.
- Experience with RTL Design tools that include design entry, synthesis, formal verification, RTL/gate level simulation, cross-domain clocking analysis and static timing analysis.
- Course and Practical usage in RTL design, design verification, synthesis & formality.
- Proficiency in SystemVerilog development languages.
- Course and Practical usage in Static Timing Analysis and Verilog simulation tools.
- Should be able to design complex state machines & data path logic.
- Proficiency in scripting languages (TCL / Perl / Python) and LINUX.
- Ability to understand and implement industry standards.
- Ability to write detailed design specifications.
- Good analytical, oral and written communication skills.
- Able to write clean, readable presentations.
- Self-motivated, proactive team player.
- Ability to work to schedule requirements.
- Preferred Master’s in Electrical Engineering, Computer Engineering or Computer Science.
- FPGA and ASIC System On Chip Design Experience.
- Lab Experience for system-level validation.
Benefits
- Competitive base pay
- Restricted stock units
- Quarterly bonus payments
- Health benefits that begin day one
- Retirement savings plans
- Industry leading ESPP program with a 2 year look back feature
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