Package Design Engineer at Teledyne e2v leading the design flow of microelectronic packages. Coordinating with teams and vendors to ensure successful design and implementation processes.
About the role
- Silicon Designer contributing to Intel's neuromorphic computing technologies through innovative design and collaboration. Focus on advanced semiconductor designs to enable AI workloads.
Responsibilities
- Model, prototype, and document new features for improving product KPIs and expanding workload breadth. Evaluate tradeoffs in partnership with architects and algorithms researchers.
- Evaluate, select, and integrate vendor IP especially for chip/chiplet interfaces.
- Enter RTL and asynchronous design (CSP/CAST) optimized for synthesis and place-and-route closure.
- Work with system software developers and architects to define runtime, boot, reset, and power management modes and requirements.
- Review test plans and work with verification engineers to debug regression/test failures.
- Work with physical design engineers on floorplans, timing constraints, and post-layout timing issues.
Requirements
- Bachelors & 9+ years or Masters & 6+ years or PhD & 4+ years with an engineering degree and hands-on design experience.
- 4+ years of experience in SoC accelerator or ASICs design.
- 4+ years of experience entering new designs from architecture specifications.
- History of enabling production quality silicon.
- Experienced in neuromorphic computing and AI/ML accelerator design.
- Experience with standard IO interfaces, PHYs, and protocols such as Ethernet, PCIE, MACsec/IPsec, RoCEv2, MIPI CSI-2, JESD204.
- Experience with Low power/UPF implementation/verification techniques.
- Experience with pre-silicon customer enablement on FPGA emulation platforms.
- Experience with security design and requirements, such as Root of Trust (RoT), secure boot, cryptographic acceleration, and FIPS.
- Experience leading silicon design/verification teams.
Benefits
- health
- retirement
- vacation
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