Package Design Engineer at Teledyne e2v leading the design flow of microelectronic packages. Coordinating with teams and vendors to ensure successful design and implementation processes.
About the role
- Physical Design Engineer at Axelera AI developing multi-core in-memory compute SoCs. Collaborating on ASIC Physical Design from RTL to GDS including automation scripting in Python.
Responsibilities
- Support synthesis, floorplanning, place and route, extraction, timing analysis, and physical verification tasks
- Participate in constraint generation, timing analysis, and optimisation
- Apply clock tree synthesis (CTS) techniques
- Integration of IPs including memories, I/Os, and embedded processors
- Work with EDA tools such as Primetime, StarRC, Fusion Compiler, Formality, Primetime, and Calibre
- Write and maintain automation scripts in Python, Tcl, or Bash to support flow development
- Debug physical design issues with support from the broader team
- Collaborate with architecture, RTL, and verification teams
Requirements
- 1-5 years of experience in Physical Design or a related field (internship or academic project experience welcome)
- BSc or MSc in Electrical & Electronic Engineering, Computer Engineering, or a related discipline
- An understanding of ASIC design flow (RTL to GDS)
- Demonstrable experience with EDA tools (Fusion Compiler Innovus, Primetime, Calibre, Redhawk)
- Experience scripting in TCL and Python
- Eagerness to learn, problem-solve, and work in a collaborative environment
- Fluent in English (spoken and written)
Benefits
- Attractive compensation package, including a pension plan
- Extensive employee insurances
- Company share options
Job title
Job type
Experience level
Salary
Not specified
Degree requirement
Tech skills
Location requirements
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