Senior Analog Layout Engineer executing custom analog layouts for critical circuit blocks. Collaborating with design teams and supporting silicon bring-up and debugging processes.
Responsibilities
Perform full‑custom analog layout for critical circuit blocks
Collaborate with analog circuit designers, CAD, and methodology teams
Support silicon bring‑up, debug, and yield improvement as needed
Requirements
BSEE or equivalent in Electrical / Electronics Engineering (preferred)
6–10 years of hands‑on experience in custom analog / mixed‑signal layout
Proven experience working in 28nm, 22nm, and/or 16nm CMOS process technologies
Strong proficiency with Cadence Virtuoso Layout Suite and Calibre (DRC, LVS, PEX)
Familiarity with low‑noise, high‑speed analog layouts
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