Hybrid Senior ASIC Physical Design Engineer, Cache Coherent Interconnects

at NVIDIA

• Job title: Senior ASIC Physical Design Engineer, Cache Coherent Interconnects
• Job type: Full Time
• Experience level: Senior
• Salary: $136,000 - $212,750 per year
• Degree requirement: Postgraduate Degree
• Location requirements: Hybrid, Santa Clara, United States

About the role

• Senior ASIC Physical Design Engineer at NVIDIA responsible for the design of CPU on-chip interconnect networks and collaborating with logic design teams. Contributing to next-generation coherent interconnects and system-level caches.

Responsibilities

• Responsible for the physical design of CPU on-chip interconnect network and last-level caches.
• Work on implementation, synthesis and timing closure while collaborating closely with the logic design team on micro-architecture definition and feasibility.
• Liaison between Logic design and Physical design teams responsible for achieving timing, area, performance and power goals of the unit.
• Help define the architecture for next-generation Nvidia coherent interconnects and system-level caches.

Requirements

• Master’s Degree in Electrical Engineering, Computer Engineering or Computer Science or equivalent experience.
• 5+ years of experience in processor or other related high-performance semiconductor designs.
• Physical design expertise including hands-on synthesis experience, timing analysis, floor-planning and in-depth knowledge of industry standard physical design tools is required.
• Physical design expertise in high-frequency interconnect/cache/core design is preferred.
• Verilog expertise is preferred as is a deep understanding of ASIC design flow including RTL design and verification, DFT, and ECO.
• Strong communication and interpersonal skills are required along with the ability to work in a dynamic, global team.

Benefits

• Equity
• Benefits