Join Accro as a Production Engineer Intern focusing on optimizing food production processes. Work on digital tools and sustainability efforts in a dynamic team.
About the role
- Senior Mixed Signal Verification Engineer at Intel overseeing clock generator IP verification and collaboration with cross-functional teams. Focusing on functional correctness of PLL/FLL designs.
Responsibilities
- Perform comprehensive functional verification of clock generator IPs including PLL/FLL
- Proactively develop test benches, verification environments, tests, and checkers/assertions
- Lead Mixed Signal Validation (MSV) activities by running AMS simulations
- Replicate, root cause, and debug complex issues in the pre-silicon environment
- Collaborate with architects, RTL developers, and analog schematic owners to improve verification
Requirements
- Bachelor's degree in Electronics / Electrical/ Computer Engineering
- 3+ years of experience in Design Verification and Validation methodologies with UVM, SystemVerilog , and industry-standard EDA tools
- 3+ years of experience in scripting languages such as Python and Perl
Benefits
- Competitive pay
- Stock bonuses
- Health insurance
- Retirement plans
- Vacation
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