Design Engineer improving upholstery products for global furniture brand Koala. Leading technical responsibility on projects and collaborating with cross - functional teams for product innovation.
About the role
- IP Logic Design Engineer developing cutting-edge IPs at Intel for data centers. Designing microarchitecture and ensuring integration quality for innovative server processors.
Responsibilities
- define, document and design the microarchitecture of IP blocks and subsystems
- own the register transfer level (RTL) development for the IP block and implement the specification for logic components
- ensure quality of design through clean design partitioning, clear microarchitectural documentation, reviewing RTL design and verification of features
- apply various strategies, tools and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals
- deliver microarchitecture specifications (MAS) document along with detailed clear block diagram, signal level description, clocking details, power and timing requirements
- review the verification plan and implementation to ensure design features are verified correctly
- support SoC customers to ensure high quality integration and verification of the IP block
- drive quality assurance compliance for smooth IP to SoC handoff
- support post-silicon activity to enable various features
Requirements
- Bachelor's Degree or Master's Degree in Electrical, Electronics or Computer Engineering
- 5+ years of experience in IP design for SoC or ASIC products
- experience in chip design with familiarity of the entire development flow from definition to tape-out
- experience in high-speed I/O protocols (e.g., PCIe, CXL, Ethernet, proprietary interconnects)
- experience with protocol conversion and coherency management between different domains (I/O and memory/coherent fabrics)
- ability to debug and resolve issues across multiple domains (I/O, coherency, ordering)
- hands-on experience with RTL design, simulation, debugging, triaging, running synthesis and timing analysis
- system simulation models and debugging RTL/tests
- experience in high-speed serial link protocols/IPs (PCIe, UPI, CXL, IOMMU etc)
- experience in computer architecture and PCIe, UPI, CXL, IOMMU, Cache Coherency protocols
- strong skills in interpreting and contributing to technical specifications
Benefits
- competitive pay
- stock bonuses
- health
- retirement
- vacation
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