Design Verification Manager leading verification projects and a high-performing team for mixed-signal ICs at Cirrus Logic. Shaping strategy and methodology in a collaborative environment.
Responsibilities
Lead and mentor a team of verification engineers to deliver ICs verified to some of the highest standards in the industry.
Work with stakeholders to define verification strategies and plans aligned with business needs.
Communicate verification status, risks, and mitigation plans clearly to engineering leadership.
Identify opportunities for improvements in verification and project execution.
Provide hands-on technical support where needed, including debugging, methodology decisions, and architectural discussions.
Requirements
Bachelor’s Degree, or above, in Electronics/Computer Science or other related discipline.
Proven track record in leading verification teams and delivering verification solutions for complex mixed-signal ICs.
Strong background in metric driven verification, including planning, requirements extraction, constrained random verification and code coverage analysis
Expertise in SystemVerilog, SVA and Testbench design with verification frameworks like UVM/OVM, e, VMM
Debugging skills for both RTL and Testbench problems
Strong ability to interpret results and resolve problems
An innovative, creative, lateral thinking problem solver
Formal verification and verification qualification techniques
Scripting experience with Python, Ruby, sh/csh, TCL, Make, Perl
Gate level (including SDF)
Power aware verification (using CPF/UPF)
Object orientated programming (OOP) - Use of OOP design patterns
Benefits
personal and professional development
a uniquely flat culture
coaching, technical and performance development to support engineers at all levels
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