Physical Design Engineer in Mobileye's VLSI team responsible for EyeQ chip design. Engaging in comprehensive VLSI development from RTL to GDS throughout SoC design.
Responsibilities
Hands-on physical design block owner from RTL to GDS.
Floorplan exploration with guidance and collaboration with front-end and architecture teams.
STA: work with FE and floor planner to manage block and top level constraints and 1st level of timing analysis.
Synthesis exploration and final synthesis netlist: Scan insertion @ synthesis, clean checks from Lint, UPF & Spyglass.
Place & Route: from Synthesis netlist to final layout and signoff verification with target to achieve best power performance and area.
Requirements
BSc or MSc degree in Computer Engineering or Electrical Engineering.
2+ years of experience in Physical Design.
Experience in scripting languages like Tcl/python/Perl/tcsh.
Team player with excellent communication skills, customer orientation, and a “can-do” attitude.
Building or maintaining implementation tools and flow – Advantage.
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