Senior Verification Engineer at SiPearl defining microprocessor verification architecture and leading a team. Collaborating with design teams, focusing on next-gen SoC validation.
Responsibilities
Define the verification platform architecture (UVM/SystemVerilog, C/C++, Python, etc.)
Develop and maintain test environments, verification benches, and functional simulations
Plan, prioritize, and track verification activities throughout the development cycle
Lead and mentor a team of verification engineers
Collaborate with system architects, design teams, and embedded software teams.
Requirements
Minimum 7–10 years of experience in ASIC/SoC verification, including 3–5 years as an architect or lead
Proficiency in SystemVerilog/UVM, VHDL/Verilog, C/C++, and Python/TCL scripting
Proven experience in team management and leading technical projects
Strong understanding of SoC architectures and communication protocols (AXI, AHB, PCIe, Ethernet, etc.)
Leadership skills, ability to unite a team, and excellent communication skills
Fluent in French and professional-level English (reading, writing, speaking).
Benefits
Annual bonus*
Meal vouchers (60% covered by SiPearl)
Health insurance (70% covered by SiPearl)
Unlimited access and prepaid sessions with a practitioner of your choice via our mental health partner app, moka.care
Technical, language and personal development training
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