Analog Engineer at Intel developing IP design collateral and optimizing analog circuits. Collaborating with teams to ensure high performance and efficiency in cutting-edge technologies.
Responsibilities
Develop and manage IP design collateral and manage IP release
Drive the design, analysis, and optimization of analog circuits
Collaborate with multidisciplinary teams to ensure leading performance, reliability, and efficiency
Generate and maintain all required design views (Liberty, LEF, GDS, Verilog, etc.)
Create timing models, power models, and variation models
Develop and maintain automation scripts for view generation
Perform comprehensive QA checks on all deliverable views
Execute regression testing on generated views
Validate timing, power, and functional models
Maintain QA documentation and test reports
Develop automation tools to streamline view generation
Requirements
Bachelors with 6 years of experience, or Master's degree, or 2+ years with a PhD in Electrical Engineering, Computer Engineering, or related field
6+ years of experience in analog circuit design
Experience in IP-collateral generation (timing, front-end, back-end, and verification flows) for analog IPs
Experience with analog behavior modeling, TX/RX block circuit design, and circuit testing
Experience with Calibre DRC and similar verification tools
Experience in circuit optimization for power, area, and performance
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