Senior Design Verification Engineer contributing to mixed-signal IC developments and verification methodology improvements. Collaborating with top engineers in a leading semiconductor company.
Responsibilities
Join our silicon design verification team and work closely with digital/analog designers, applications engineers, and embedded software developers, participating in all aspects of verification for complete mixed-signal IC developments of innovative solutions.
You will work on complex verification systems and contribute to improvements in verification methodology while working alongside some of the most talented engineers in our industry.
Requirements
MS or PhD in Electrical Engineering or Computer Engineering.
At least 5+ years of experience in silicon design or verification.
Strong background with HDLs (e.g. Verilog, VHDL) and HVLs (e.g. SystemVerilog/UVM, OVM, AVM, Vera).
Strong knowledge base of digital design & systems architecture.
Able to work closely with digital/analog designers, applications engineers, and software to support both pre-silicon verification and post-silicon validation efforts.
Knowledge of signal processing and Verilog Assertions.
Ability to mentor junior engineers in verification methodology.
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