Staff Design Verification Engineer at d-Matrix focusing on hardware innovation and AI-driven solutions. Collaborating in a dynamic startup environment with a skilled team to tackle engineering challenges.
Responsibilities
We want to build a company and a culture that sustains the tests of time.
We offer the candidate a very unique opportunity to express themselves and become a future leader in an industry that will have a huge influence globally.
We are striving to build a culture of transparency, inclusiveness, and intellectual honesty while ensuring all our team members are always learning and having fun on the journey.
The candidate will get to work on a pathbreaking architecture with a highly experienced team that knows what it takes to build a successful business.
Requirements
BS in Electrical Engineering, Computer Science, or a related field with 7+ years of industry experience, or an MS in Electrical Engineering, Computer Science, or a related field with 5+ years of industry experience preferred.
Experience in SoC verification cycle from architecture to tape-out to bring-up.
Good knowledge of verification methodologies such as UVM/OVM, etc.
Hands-on ASIC-SoC design verification tests and debug experience.
Fluency with SystemVerilog randomization constraints, coverage, and assertions methodology.
Good problem-solving skills and the passion to take on challenges (particularly in AI domain).
Good experience with SystemVerilog and verification methodology (UVM/OVM/VMM).
Passionate about AI and thriving in a fast-paced and dynamic startup culture.
Benefits
Our culture is one of respect and collaboration.
We value humility and believe in direct communication.
Our team is inclusive, and our differing perspectives allow for better solutions.
We are committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work.
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