EDA Software R&D Engineer developing algorithms for RTL synthesis and digital logic optimization. Collaborating with teams to enhance hardware design productivity with innovative software solutions.
Responsibilities
Invent and develop new algorithms for RTL synthesis, digital logic optimization, graph-based RTL traversal, analysis, and manipulation.
Build physical-aware synthesis techniques using placement/congestion/timing feedback to improve PPA.
Develop strategies for rapidly analyzing the RTL change impact on timing, power, area, and impact to DFT, clocking, and power delivery on design.
Prototype and evaluate ML methods (e.g., GNNs, RL, models) to guide optimization decisions; integrate successful approaches into production.
Explore high performance algorithms for clustering, min cost tree covering (technology mapping), datapath implementation and other details of logic synthesis, especially that efficiently incorporate human insight.
Collaborate with design teams to facilitate deployment of solutions and actively drive the roadmap of increasing hardware design productivity.
Requirements
MS or PhD in Electrical Engineering or Computer Science or equivalent experience
6+ years experience in EDA software and/or VLSI flows, with significant work in logic synthesis or digital optimization.
Strong CS fundamentals and modern C++ experience (templates/STL, concurrency libraries, profiling and performance optimization, data structures, algorithms, performance, concurrency, testing).
Solid understanding of RTL (Verilog/SystemVerilog) and digital design concepts (timing, clocking, DFT basics, power intent).
Expertise in EDA techniques, including logic synthesis, global route, static timing analysis, power & area optimization and SAT solvers
Good communication and interpersonal skills.
Benefits
equity
benefits
Job title
Senior Software R&D Engineer, Digital Logic Synthesis
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