Memory Subsystem Architect at Micron focusing on next-gen HBM DRAM products. Collaborating with varied teams to innovate memory subsystem architectures.
Responsibilities
Design & develop next generation HBM DRAM products
Collaborate with internal and external partners to develop novel architectures and detailed IP requirements
Lead engagement with IP vendors, including evaluation and selection of interface and functional IP
Analyze benchmarks, workloads, and simulations to identify opportunities for performance, efficiency, and architectural innovation
Partner with RTL, validation, and product teams to ensure timely and successful implementation
Drive microarchitecture definition and participate in performance simulation and benchmarking
Requirements
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
Minimum of 15 years of experience in memory subsystem architecture and design
Deep understanding of memory controller design and memory types (DDR, LPDDR, GDDR, HBM)
Experience with PHY design and understanding of signal integrity issues
Proficiency in Network-on-Chip (NoC) architecture and design
Familiarity with industry-standard bus protocols such as AXI, AMBA, AHB, DFI, etc.
Strong analytical and problem-solving skills
Excellent written and verbal communication skills.
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